Introduction
Disaggregation is an emerging compute paradigm that splits existing monolithic servers into a number of consolidated single-resource pools that communicate over a fast interconnect. This model decouples individual hardware resources, including tightly coupled ones such as processors and memory, and enables the composition of logical compute platforms with flexible and dynamic hardware configurations.The concept of disaggregation is driven by various recent trends in computation. From an application perspective, the increasing importance of data analytics and machine learning workloads in HPC centers brings unprecedented need for memory capacity, which is in stark contrast with the growing imbalance in the peak compute-to-memory capacity ratio of traditional system board based server platforms where memory modules are co-located with processors. Meanwhile, traditional simulation workloads leave memory underutilized. At the hardware front, the proliferation of heterogeneous, special purpose computing elements promotes the need for configurable compute platforms, while at the same time, the increasing maturity of optical interconnects raises the prospects of better distance independence in networking infrastructure.
The workshop intends to explore various aspects of resource disgregation, composability and their implications for high performance computing, both in dedicated HPC centers as well as in cloud environments. RESDIS aims to bring together researchers and industrial practitioners to foster discussion, collaboration, mutual exchange of knowledge and experience related to future disaggregated systems.
Call for Papers
- Operating systems and runtime support for disaggregated platforms
- Simulation of disaggregated platforms with existing infrastructure
- Runtime systems and programming abstractions for disaggregation and composability
- Networking for disaggregation, including silicon photonics and optical interconnects
- Implications of resource disaggregation for scientific computing and HPC applications
- Algorithm design for disaggregated and composable systems
- Disaggregated high throughput storage
- Disaggregated heterogeneous accelerators (GPUs, FPGAs, AI Accelerators, etc.)
- Resource management in disaggregated and composable platforms
The workshop proceedings will be published electronically via the IEEE Computer Society Digital Library. Submitted manuscripts must use the proceedings templates at: https://www.ieee.org/conferences/publishing/templates.html. Submissions must be between 5 and 8 pages, including references and figures. Prospective authors should submit their papers in PDF format through Linklings’ submission site:
Important Dates
Submission deadline
Acceptance notification
Camera ready paper deadline
Workshop date
Organization
Workshop Chairs
Program Committee (tentative)
Sandia National Laboratories, USA
Nvidia, USA
IMDEA Software Institute, Spain
Illinois Institute of Technology, USA
Oak Ridge National Laboratory, USA
KTH Royal Institute of Technology, Sweden
Fujitsu, Japan
Télécom SudParis, France
Agenda
All times in Central Time Zone (UTC-5)
TBA
Event Venue
America's Center Convention Complex, 701 Convention Plaza, St. Louis, MO 63101
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