IntroductionDisaggregation is an emerging compute paradigm that splits existing monolithic servers into a number of consolidated single-resource pools that communicate over a fast interconnect. This model decouples individual hardware resources, including tightly coupled ones such as processors and memory, and enables the composition of logical compute platforms with flexible and dynamic hardware configurations.
The concept of disaggregation is driven by various recent trends in computation. From an application perspective, the increasing importance of data analytics and machine learning workloads in HPC centers brings unprecedented need for memory capacity, which is in stark contrast with the growing imbalance in the peak compute-to-memory capacity ratio of traditional system board based server platforms where memory modules are co-located with processors. At the hardware front, the proliferation of heterogeneous, special purpose computing elements promotes the need for configurable compute platforms, while at the same time, the increasing maturity of optical interconnects elevates the prospects of better distance independence in networking infrastructure.
The workshop intends to explore various aspects of resource disgregation, composability and their implications for high performance computing, both in dedicated HPC centers as well as in cloud environments. RESIDS aims to bring together researchers and industrial practitioners to foster discussion, collaboration, mutual exchange of knowledge and experience related to future disaggregated systems.
Call for Papers
- Operating systems and runtime support for disaggregated platforms
- Simulation of disaggregated platforms with existing infrastructure
- Runtime systems and programming abstractions for disaggregation and composability
- Networking for disaggregation, including silicon photonics and optical interconnects
- Implications of resource disaggregation for scientific computing and HPC applications
- Algorithm design for disaggregated and composable systems
- Disaggregated high throughput storage
- Resource management in disaggregated and composable platforms
The workshop proceedings will be published electronically via the IEEE Computer Society Digital Library. Submitted manuscripts should be formatted using the IEEE template conference mode. The maximum paper length is 8 pages, not including references and other appendices. Prospective authors should submit their papers in PDF format through Linklings’ submission site:
5th 19th (Fri) AoE
Submission deadline (extended)
Final paper deadline
Intel Corporation, USA & RIKEN, Japan
Lawrence Berkeley National Laboratory, USA
Columbia University, USA
Massachusetts Institute of Technology, USA
Columbia University, USA
Oak Ridge National Laboratory, USA
Lawrence Livermore National Laboratory, USA
Télécom SudParis, France
All times in Central Daylight Time (UTC-5)
Opening Distinguished Lecture: Putting Memory and Computing in a Single Pool over Compute Express Link
Prof. Myoungsoo Jung (Korea Advanced Institute of Science and Technology)
Nan Ding (LBNL), Samuel Williams (LBNL), Hai Ah Nam (NERSC), Taylor Groves (NERSC), Muaaz Gul Awan (NERSC), Christopher Delay (NERSC), Oguz Selvitopi (LBNL), Leonid Oliker (LBNL), Nicholas Wright (NERSC)
Hasan Maruf (University of Michigan)
Daniel Berger (Microsoft Corporation)
Debendra Das Sharma (Intel Corporation)
Room D172, Kay Bailey Hutchison Convention Center Dallas, TX, USA
Kay Bailey Hutchison Convention Center
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The convention center is located just 30 minutes from Dallas/Fort Worth International (DFW) airport and seven minutes from Dallas Love Field (DAL) airport, with several public transportation options readily available. Dallas Area Rapid Transit (DART) has a light rail station at the convention center, and a free D-Link shuttle bus to area shopping and entertainment.
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