Introduction
Disaggregation is an emerging compute paradigm that splits existing monolithic servers into a number of consolidated single-resource pools that communicate over a fast interconnect. This model decouples individual hardware resources, including tightly coupled ones such as processors and memory, and enables the composition of logical compute platforms with flexible and dynamic hardware configurations.The concept of disaggregation is driven by various recent trends in computation. From an application perspective, the increasing importance of data analytics and machine learning workloads in HPC centers brings unprecedented need for memory capacity, which is in stark contrast with the growing imbalance in the peak compute-to-memory capacity ratio of traditional system board based server platforms where memory modules are co-located with processors. Meanwhile, traditional simulation workloads leave memory underutilized. At the hardware front, the proliferation of heterogeneous, special purpose computing elements promotes the need for configurable compute platforms, while at the same time, the increasing maturity of optical interconnects raises the prospects of better distance independence in networking infrastructure.
The workshop intends to explore various aspects of resource disgregation, composability and their implications for high performance computing, both in dedicated HPC centers as well as in cloud environments. RESDIS aims to bring together researchers and industrial practitioners to foster discussion, collaboration, mutual exchange of knowledge and experience related to future disaggregated systems.
Call for Papers
The RESDIS program committee solicits original, high-quality submissions
of unpublished results related to the theme of resource disaggregation
and composable systems.
Topics of interest include, but not limited to:
Workshop papers will be published in the SC Workshops Proceedings volume.
All papers submitted for the official proceedings must use the IEEE proceedings template (two-column, US letter, conference mode).:
https://www.ieee.org/conferences/publishing/templates.
Submissions must be at least 5 pages (no upper limit), including references and figures. Prospective authors should submit their papers in PDF format through Linklings’ submission site:
Submissions closed
- Disaggregated hardware in high-performance computing
- Operating systems and runtime support for disaggregated platforms
- Simulation of disaggregated platforms with existing infrastructure
- Runtime systems and programming abstractions for disaggregation and composability
- Networking for disaggregation, including silicon photonics and optical interconnects
- Implications of resource disaggregation for scientific computing and HPC applications
- Algorithm design for disaggregated and composable systems
- Disaggregated high throughput storage
- Disaggregated heterogeneous accelerators (GPUs, FPGAs, AI Accelerators, etc.)
- Resource management in disaggregated and composable platforms
- Operating systems and runtime support for disaggregated platforms
- Simulation of disaggregated platforms with existing infrastructure
- Runtime systems and programming abstractions for disaggregation and composability
- Networking for disaggregation, including silicon photonics and optical interconnects
- Implications of resource disaggregation for scientific computing and HPC applications
- Algorithm design for disaggregated and composable systems
- Disaggregated high throughput storage
- Disaggregated heterogeneous accelerators (GPUs, FPGAs, AI Accelerators, etc.)
- Resource management in disaggregated and composable platforms
Workshop papers will be published in the SC Workshops Proceedings volume.
All papers submitted for the official proceedings must use the IEEE proceedings template (two-column, US letter, conference mode).:
https://www.ieee.org/conferences/publishing/templates.
Submissions must be at least 5 pages (no upper limit), including references and figures. Prospective authors should submit their papers in PDF format through Linklings’ submission site:
Important Dates
Submission deadline (Extended/Final)
Acceptance notification
Camera ready paper deadline
Workshop date
Organization
Workshop Chairs
Program Committee
Michael Aguilar
Sandia National Laboratories, USA
Kyle Hale
Illinois Institute of Technology, USA
John (Jack) Lange
Oak Ridge National Laboratory, USA
George Michelogiannakis
Lawrence Berkeley National Laboratory, USA
Ivy Peng
KTH Royal Institute of Technology, Sweden
Christian Pinto
IBM Research Europe, Ireland
Yu Tanaka
Fujitsu, Japan
Gaël Thomas
Télécom SudParis, France
Agenda
All times in Central Standard Time (CST, UTC-6)
Monday, November 16, 2026
9:00 AM - 12:30 PM, Room W181b
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Workshop Opening
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Opening Invited Talk: Tightly Coupled and Customizable Heterogeneity
Samantika Sury (HPE Fellow, Vice President, and Chief Hardware Architect for HPC and AI Infrastructure Solutions)
Abstract: The slowing of Moore’s Law and the rapid growth of AI are pushing systems toward greater specialization across compute, memory, networking, and storage. At the same time, AI for Science is bringing simulation, analytics, training, inference, and agentic execution into increasingly connected workflows that need to share and move data efficiently. No single architecture is well suited to every part of these workflows.
This talk looks at tightly coupled and customizable heterogeneity as a way to build systems around these changing needs. A key focus will be macroheterogeneity, where different computing architectures work together as part of a larger system and each part of a workflow can run where it fits best. We will also look at customizable scale-up hypernodes, bringing compute, memory, accelerators, and high-bandwidth fabrics together in configurations shaped by workload needs. The goal is not simply to add more forms of heterogeneity, but to make them easier to couple, customize, and use as part of an end-to-end AI-HPC system.
Bio: Samantika Sury serves as an HPE Fellow, Vice President, and Chief Hardware Architect for HPC and AI Infrastructure Solutions. She leads the Future Technologies team, which focuses on advancing hardware and software system innovations. Samantika has previously held prominent technical leadership roles at Samsung and Intel® driving silicon and system architecture innovations into marketable products. Samantika holds 31 U.S. and international patents and has published more than 25 peer-reviewed papers. She was recognized in HPCWire People to Watch 2026.
This talk looks at tightly coupled and customizable heterogeneity as a way to build systems around these changing needs. A key focus will be macroheterogeneity, where different computing architectures work together as part of a larger system and each part of a workflow can run where it fits best. We will also look at customizable scale-up hypernodes, bringing compute, memory, accelerators, and high-bandwidth fabrics together in configurations shaped by workload needs. The goal is not simply to add more forms of heterogeneity, but to make them easier to couple, customize, and use as part of an end-to-end AI-HPC system.
Bio: Samantika Sury serves as an HPE Fellow, Vice President, and Chief Hardware Architect for HPC and AI Infrastructure Solutions. She leads the Future Technologies team, which focuses on advancing hardware and software system innovations. Samantika has previously held prominent technical leadership roles at Samsung and Intel® driving silicon and system architecture innovations into marketable products. Samantika holds 31 U.S. and international patents and has published more than 25 peer-reviewed papers. She was recognized in HPCWire People to Watch 2026.
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Past the FLOPS Era: Memory-Bandwidth Disaggregation as a Design-Space Coordinate for LLM Accelerators
Bambi DeLaRosa (Micron Technology), Katya Giannios (Micron Technology), Khalid Ahmad (Micron Technology)
Abstract: Accelerator memory hierarchies assume a single high-bandwidth pool sized for weights, but long-context LLM inference violates that assumption: key/value cache bandwidth demand overtakes weights at production batch sizes. Weights and per-request state are physically distinct traffic sources — static and shared versus per-request and grow-in-place — that contend only under the single-pool model. We propose a coordinate system that characterizes any accelerator by two bandwidth scalars (βw, βs) and any workload by state-to-weight ratio ρ(n) and per-token weight reuse r. Per-decode latency splits into two independently provisioned pools, and a local-minimum theorem proves the shared-pool corner is strictly dominated past b·ρ(n) = 1, with the penalty bounded by 2×. Across a 21,609-point design space, only 0.39% of feasible designs land within 10% of optimal, while the best two-tier design gains 25.6%. The contribution is a coordinate system in which memory-centric codesign can be reasoned about in hardware coordinates.
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Morning Break
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CoDISAR: A Composable Disaggregated Infrastructure for SAR Backprojection
Jacob Wong (Queen's University), Curtis Shorts (Queen's University), Boniface Yogendran (Defense research and Development Canada), Ryan Grant (Queen's University)
Abstract: Synthetic Aperture Radar (SAR) is a remote sensing technology, used on moving platforms such as aircraft. Challenges arise when generating high-resolution images due to the computational complexity of image reconstruction algorithms. Traditional approaches generate the images offline or deploy high-throughput hardware onboard the aircraft. Onboard compute is restricted by drone constraints including size, weight, and power. We propose CoDISAR, a solution where accelerators are distributed in the field, accessible via composable disaggregated infrastructure. This enables drone swarms to support high-resolution SAR imaging in near-real time, where drones can request GPUs from pools of resources. We examine the effects on time-to-image for the backprojection algorithm using distanced accelerators. Network latencies attributed to distances of up to 1000 km are inserted to evaluate the performance of CoDISAR against typical compute resources available on drones. Modeling indicates that our solution can generate high-resolution images up to 3.89x faster over classical methods.
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Congestion-Aware Collective Communication for Composable Disaggregated GPUs
Amirreza Barati Sedeh (Queen's University), Ryan Eric Grant (Queen's University), Ahmad Afsahi (Queen's University)
Abstract: Traditional server-centric data center design relies on a fixed ratio of compute and memory, limiting adaptability to evolving workloads, particularly in AI. Composable Disaggregated Infrastructure (CDI) addresses this by enabling on-demand composition of disaggregated devices. We focus on the intersection of GPU disaggregation and MPI collective communications, introducing an emulation methodology that uses available hardware to emulate PCIe-based disaggregated GPUs. While high-end servers run collectives over high-bandwidth intra-node interconnects, PCIe-based disaggregated systems introduce congestion, making it challenging to identify the best-performing algorithm for each collective. We propose a congestion-aware scoring model that estimates congestion at step granularity and, grounded in a Hockney-based bandwidth model, predicts the absolute communication latency of each algorithm on different PCIe topologies. Experimental results show the model predicts absolute latency within an average accuracy of 94.73%, 93.25%, and 93.94% for Allgather, ReduceScatter, and Alltoall, respectively, providing an effective, profiling-free tool for algorithm selection in GPU-disaggregated systems.
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Impact of Overheads in Disaggregated Systems on Job Turnaround Times
Shinji Yoshida (The University of Osaka), Keichi Takahashi (The University of Osaka), Susumu Date (The University of Osaka)
Abstract: Disaggregated systems dynamically attach accelerators to and detach them from compute nodes over a network. They can thus allocate the exact number of accelerators requested by each job, reducing idle accelerators. However, resource disaggregation incurs two overheads. The communication latency between compute nodes and accelerators increases the execution times of jobs, and the reconfiguration to attach and detach accelerators takes time. These overheads may make job turnaround times longer, but their effects remain unclear. We investigate their effects using a scheduling simulator we developed for disaggregated systems. The results show that an approximately 20% increase in execution times, reconfiguration times of 90 seconds or longer, and a shortage of accelerators make turnaround times longer than those in traditional systems. We also show that introducing fixed compute nodes, to which accelerators remain attached and require no reconfiguration, reduces turnaround times. We finally summarize considerations for administrators adopting disaggregated systems.
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Towards Server-Grade Device Pooling over Routable PCIe with Improved and Scalable Systems Software
Magnus Kalland (Dolphin ICS, Simula Research Laboratory), Jonas Markussen (Dolphin ICS), Lars Kristiansen (Dolphin ICS), Carsten Griwodz (University of Oslo), Tore Larsen (Simula Research Laboratory), Håkon Stensland (Simula Research Laboratory), Tor Skeie (Simula Research Laboratory and University of Oslo)
Abstract: Routable PCIe enables composable infrastructures and device pooling with native drivers, yet little is known about its end-to-end performance in production systems, leaving a gap between microbenchmark research and marketing whitepapers. We show routable PCIe challenges assumptions made by traditional operating systems, particularly in how DMA buffers are managed when accessed by remote devices. We resolve a cache incoherence issue in the IOMMU's interrupt remapping subsystem and adapt IOMMU scalability optimizations from the OS kernel to routable PCIe software, reducing median DMA deallocation latency by 90% versus prior work and enabling full parallelism for pooled devices. We further optimize the deallocation critical path via a novel IOMMU sidecore-offloading scheme, reducing median unmapping latency by 26% and tail latency by up to 89% compared to the kernel. Finally, we evaluate on server-grade storage and GPUs, showing routable PCIe achieves native IOPS at lower latency and CPU utilization than scale-out alternatives.
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Green Shift: Resize the GPU, Not the Process
Aditya Dhakal (HPE), Gourav Rattihalli (HPE), Joseph Wright (HPE), Harumi Kuno (HPE), Dejan Milojicic (HPE)
Abstract: GPUs are multiplexed across workloads using NVIDIA MPS, MIG, and CUDA Green Contexts. Multiplexing maximizes utilization while isolation keeps tail latency predictable. But MPS and MIG are inefficient: resizing a partition requires restarting the bound processes and reloading model weights and state, incurring seconds of idle downtime that grows with model size. This poorly fits modern inference, where many models share a GPU and their compute demands shift constantly.
Green Contexts instead change a process’s Streaming-Multiprocessors (SMs) budget on the fly, with no restart or reload, lowering reconfiguration time and GPU idle gaps. However, they target intra-application resource management, lack notion of multi-tenancy, and are not natively supported in PyTorch/vLLM. We introduce GreenShift, which repurposes Green Contexts for multi-tenant inference. On an NVIDIA H100, GreenShift cuts a large model’s reconfiguration downtime from roughly 30s to ~3s (>10× reduction), and uses ~1.5 to 2× less energy during the resize than MPS.
Green Contexts instead change a process’s Streaming-Multiprocessors (SMs) budget on the fly, with no restart or reload, lowering reconfiguration time and GPU idle gaps. However, they target intra-application resource management, lack notion of multi-tenancy, and are not natively supported in PyTorch/vLLM. We introduce GreenShift, which repurposes Green Contexts for multi-tenant inference. On an NVIDIA H100, GreenShift cuts a large model’s reconfiguration downtime from roughly 30s to ~3s (>10× reduction), and uses ~1.5 to 2× less energy during the resize than MPS.
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